a. Field of the Invention
The present invention is concerned with a vertical-type junction field effect transistor, and more particularly, it pertains to an improved manner of forming the gate region of a vertical-type junction field effect transistor.
B. Description of the Prior Art
Of late, there has been animately progressing researches on field effect transistors exhibiting unsaturated drain voltage-drain current characteristics closely resembling those of a triode.
As a result of these research efforts, there has been recently proposed a vertical-type junction field effect transistor as shown in FIG. 1. This known field effect transistor is prepared by the steps of: selectively diffusing, for example, a highly concentrated p-type impurity into the drain region 4 made of an n-type semiconductor of a low impurity concentration on one surface thereof, to form a gate region 6 the gate region is in such a form that it is buried in said drain region 4. On top of the drain region 4 containing said gate region 6a source region is formed by chemical vapor-deposition technique. The source region 8 is composed of an n-type semiconductor of an impurity concentration not lower than that of the drain region 4. On top of the base region 6' of the gate electrode of said gate region 6 a gate electrode lead-out layer 10 is formed together with ohmic-connecting electrodes to the gate, source and drain regions, respectively, by the diffusion technique. The gate electrode lead-out layer 10 is of a low resistance.
Such a known junction field effect transistor, however, has several problems that have to be solved. More specifically, the gate region 6 is formed by diffusing, through the openings of a mask, a required impurity into the drain region 4. However, this impurity spreads in the horizontal as well as in the vertical directions. This spreading of the impurity results in an increase in the width and depth of the gate grid 6. As a result, there arise the disadvantages that the junction capacitance increases and that the upper limit of operating frequency is lowered. On the other hand, in order to highten the upper limit of operating frequency, it is necessary to sufficiently enhance the impurity concentration of the gate region 6 to thereby reduce the series resistance at the gate region. In view of the nature of the diffusion method, however, the local maximum impurity concentration of the gate region 6 tends to become markedly high when it is intended to elevate the mean impurity concentration. Therefore, crystal defect is apt to develop at the intersurface between the drain region 4 and the source region 8, especially at the sites adjacent to the gate regions 6. This development of crystal defect, in turn, increases reverse leakage and brings about a degradation of the breakdown voltage. By relying on the conventional gate constructing techniques, the gate region tends to have an excessively high impurity concentration, which, in turn therefore, results in the undesirable closing of the gate apertures due mainly to the surface diffusion of the impurity. Furthermore, the drain region 4 is formed usually by relying on the vapor deposition technique. However, there is a need that the thickness of the drain region 4 be augmented by the amount of depth of the deposited gate region 6. Thus, the time which is required for forming the drain region 4 increases in length corresponding to the augmented thickness of this region to such an extent that the development of a crystal defect might result.